FIG. 20 is a plan view of memory cells of a semiconductor DRAM. As shown in FIG. 20, the memory cells of the DRAM have word lines (transfer gate) 106a formed on a semiconductor wafer 101, and bit lines 106b formed above the word lines 106a. Therefore, a bit line contact 112 is disposed between the word lines 106a so as to extend near the word lines 106a down to the wafer 101.
A stacked capacitor is disposed above the bit line 106b. A contact 114 included in the capacitor, i.e., a storage node 113, is disposed in a space of a lattice of the word lines 106a and the bit lines 106b in an active region 115 so as to extend near the bit lines and the word lines down to the wafer 101.
FIGS. 21(a), 21(b) and 21(c) are sectional views of a contact in the DRAM, taken on line A–A′, B–B′ and C–C′, respectively, in FIG. 20. As shown in FIGS. 21(a), 21(b) and 21(c), the word line 106a is formed on the semiconductor wafer 101, and the bit line 106b is disposed between a lower oxide film 103a and an upper oxide film 103b. 
As techniques for forming minute lattices for semiconductor devices advance, the control of pattern superimposition and dimensional errors grows more difficult. For example, if patterns are not superimposed correctly, a bit line contact 112 or a storage node contact 113 can be accidentally connected to the word line 106a or the bit line 106b in a region enclosed by an ellipse indicated by a dotted line. Therefore, the contact must be formed in a smaller diameter or be formed by a self-aligning contact technique which forms a contact so that the contact may not accidentally be connected to a wiring line, even if the contact overlaps the wiring line.
FIGS. 22(a) to 22(c) illustrate, by way of example, self-alignment contact structures employing a nitride film. FIG. 22(a) illustrates a self-alignment contact structure of a blanket SiN system, using a silicon nitride film (SiN film) 108 formed between interlayer insulating oxide films 107 and 103. FIG. 22(b) illustrates a self-alignment contact structure of a SiN side wall system, using silicon nitride films 108 covering the side surfaces of a word line 106a. FIG. 22(c) illustrates a self-alignment contact structure of a SiN covered line system, using a silicon nitride film 108 covering the upper and side surfaces of a word line 106a. In these self-alignment contact structures, the word line (transfer gate) 106a is covered with the SiN film 108, i.e., an etching resistant film. In the self-alignment contact structure of a blanket SiN system, etching of the silicon dioxide film is temporarily stopped by the SiN film 108. The SiN film 108 and the underlying oxide film are then etched to form a hole reaching to the wafer 101. In the self-alignment contact structure of a SiN side wall system and the self-alignment contact structure of a SiN covered line system, oxide films are etched without also etching the SiN film 108 on the side surfaces, to form a hole reaching to the wafer 101.
The lateral size of the contacts of the foregoing DRAM has progressively been reduced, and the trend is towards the progressive reduction of the design diameter of holes. However, the longitudinal thickness of the films has scarcely been reduced so that the parasitic capacity between the wiring lines will not increase. Therefore, the aspect ratio, i.e., the ratio of the depth of a contact hole to the diameter of the same, increases. In fine contact holes, there arises RIE lag, i.e., the reduction of etching rate at the bottom of a contact hole of a large aspect ratio. (Refer to, for example, J. Vac. Sci. Tech. B10(5), 1994)
FIGS. 23(a) and 23(b) are sectional views of contact holes for illustrating problems that may arise when forming a contact hole of a large aspect ratio. FIG. 23(a) shows an etching stop phenomenon, which occurred at the bottom of a contact hole of a large aspect ratio when forming the contact hole in a portion of an interlayer insulating film 103, corresponding to an opening formed in a resist film 110. Such an etching stop phenomenon can be avoided by enhancing an isotropic etching component. However, it is possible that the interlayer insulating film 103 is etched laterally as shown in FIG. 23(b), and a wiring line 106b, such as a bit line, formed within the interlayer insulating film 103, is exposed in the contact hole and is accidentally connected to a contact formed in the contact hole.
FIGS. 24(a) and 24(b) are views for illustrating problems that may arise in forming a contact between wiring lines in the self-alignment contact structure of a blanket SiN system. FIG. 24(a) illustrates an etching stop phenomenon which occurred in an opening formed in a gap in a SiN film 108. FIG. 24(b) illustrates the formation of a bottom portion of a large aspect ratio in a hole, when an opening is misaligned.
A self-alignment system using a silicon nitride film as an etching stopper film forms a nitride film, which is hard to etch, in the bottom of a deep contact hole liable to cause RIE lag, and the aspect ratio of the bottom portion of the contact hole narrowed by the nitride film is increased and is liable to cause incomplete etching. If faulty superimposition is made, the bottom portion of the contact hole is further narrowed toward the bottom and an unetched portion of the interlayer insulating film is liable to remain due to incomplete etching. Consequently, a defect due to no contact or contact of an increased resistance occurs owing to the incorrect contact hole.
A method of forming a silicon dioxide film as an interlayer insulating film without forming any steps in contact holes is disclosed in, for example, JP-A No. 1-274419. This prior art method, however, is not satisfactory in forming contact holes of a large aspect ratio.